Community Newsletter: February 2018
IN THIS ISSUE:
- Message from the Chair
2017 in review and a look toward what’s to come in 2018
- Upcoming Accellera Events
DVCon U.S. and DVCon China are around the corner
- UVM Working Group Update
WG Chair Justin Refice provides insight into the group's activities
- Technical Spotlight
SystemC CCI Configuration is in public review
- New Portable Stimulus Community
Access to the latest information and forum activity
- SystemC Verification 2.0.1
New version now available for download
- SystemRDL 2.0
New version now available for download
- In the News
Accellera’s 2018 Leadership team is in place
Message from the Chair
As I look back at 2017 and my first year as Accellera Chair, I would first like to thank all of our volunteers for their tremendous contributions and dedication to our standards efforts throughout the year. With their help, we continue to provide ongoing standards development as well as updates to our current standards, quality documentation, and online support to our communities in our forums. We have a proven track record of standards acceptance in the IEEE Standards Association and adoption through our Accellera-sponsored IEEE Get Program.
Standards are a critical building block in new technologies and product development. Through our technical conferences and online forums, we provide a resource for education and answers to key technical questions faced by design and verification engineers on a daily basis.
Many of our working groups have put in a great deal of time and effort to get their standards to the next stage of development. The UVM-SystemC 1.0-beta release recently completed a public review period, and SystemC CCI 1.0 is currently in public review. SystemC Verification 2.0.1 and SystemRDL 2.0 have recently been released for download.
This is an exciting year at Accellera. New standards in 2018 include Portable Stimulus 1.0, SystemC CCI 1.0, and SystemRDL 2.0. In addition, we will have our SystemC AMS and IP-XACT User Guides available this year. Also, the Multi-Language Working Group has a skeleton demo in the works.
Our Board of Directors and Officers are in place for 2018 and we recently announced that board members Martin Barnasconi from NXP Semiconductors will chair our Technical Committee and Dennis Brophy from Mentor, A Siemens Business, will chair our Promotions Committee. This will help facilitate board member involvement in Accellera’s day-to-day activities and better align the two groups for planning and promotion.
As we look toward the future and continue to evolve with the needs in the industry, there are many new standardization opportunities with the development of autonomous driving, evolution of the IoT, and an increased emphasis on RF/A integration and system-level design and verification. We look forward to addressing the next emerging standards challenges.
We continue to evolve and grow our DVCon brand to reach more engineers around the globe and fine-tune each conference to best suit the needs of the region. In the first half of this year we have DVCon U.S., which is celebrating its 30th year serving the needs of the design and verification community. Building upon the success of the inaugural DVCon China 2017, we also have an exciting program in the works for DVCon China 2018.
Wishing you a prosperous 2018!
Lu Dai, Accellera Systems Initiative Chair
Upcoming Accellera Events
DVCon U.S. 2018
“This year DVCon U.S. reaches an important milestone as it enters its 30th year of bringing advances in design languages and verification methods to the design and verification community,” stated Dennis Brophy, DVCon U.S. 2018 general chair. “The challenges brought by ever increasing design complexity continue to promote the development of novel solutions and methods. One driver of this is the growing demand from new end-user markets. As this demand grows, DVCon U.S. is growing to address it.”
Accellera Day opens DVCon U.S. 2018 on Monday, February 26th with a full morning tutorial on the latest emerging standard from Accellera: “Portable Test and Stimulus: The Next Level of Verification Productivity is Here.” The tutorial will be followed by an Accellera-sponsored luncheon featuring a presentation by Accellera chair Lu Dai that will include an Accellera update, the presentation of the Accellera Technical Excellence Award, a look at the upcoming worldwide DVCon events, and the latest news on working group activities. Following the presentation, a panel of Accellera working group chairs will give brief updates on their working groups, including a Q&A session with the attendees.
Monday afternoon will be filled with a tutorial, “IEEE-Compatible UVM Reference Implementation and Verification Components,” that will introduce engineers to the new reference implementation aligned with IEEE 1800.2 created by the Accellera UVM Working Group.
The Keynote, “Industry’s Next Challenge: The Petacycle Challenge,” will be presented by Christopher Tice, vice president of Verification Continuum Solutions in the Verification Group at Synopsys, on Tuesday, February 27th. In addition to the 39 papers, 33 posters, 8 tutorials and 2 panels throughout the week, new to DVCon U.S. this year are four 90-minute short workshops designed to give smaller companies more opportunities to participate in the program.
A hallmark of DVCon is the opportunity to interact with peers and experts in the industry. In addition to the breaks throughout the program, the Expo will be held Monday from 5:00-7:00pm and Tuesday and Wednesday from 2:30-6:00pm, followed by receptions each evening with plenty of opportunities to connect with colleagues.
For the complete DVCon U.S. 2018 schedule, visit www.dvcon.org. To register, visit here.
Gabe Moretti summarizes what’s in store for DVCon U.S. 2018: For a more in-depth look into what you can look forward to at DVCon U.S. 2018, read Gabe Moretti’s article “DVCon US 2018 is Bigger and Better” in EDA Café.
DVCon China 2018
The first DVCon China was a success with over 200 attendees at the inaugural event. The Steering Committee is working hard on the program for DVCon China 2018 to be held April 18th at the Doubletree by Hilton Shanghai-Pudong. Attendees will be able to attend a variety of technical sections covering topics such as System-Level Design, Verification & Validation, IP Reuse and Design Automation, Mixed-Signal, Low Power, High Performance Design and Verification, and Virtual Prototyping. Attendees can also visit the Expo and interact with peers and experts from many different companies. The full program is now available. Advance registration is available through March 16th.
An Update on UVM from Working Group Chair Justin Refice
The UVM Working Group was formed almost a decade ago to develop a standard to improve interoperability and make it easier to reuse verification components, helping to lower verification costs and improve design quality. During that time, UVM has built upon the SystemVerilog standard and become an important companion to it.
In 2015 we submitted UVM 1.2 as a contribution to the IEEE P1800.2 Working Group, and on April 11, 2017 the IEEE-SA approved the IEEE 1800.2 Standard for UVM.
With the ongoing maintenance of the standard now in the hands of the IEEE-SA, the UVM Working Group’s focus has shifted towards developing a reference implementation aligned with IEEE 1800.2. The IEEE 1800.2 standard contains changes that make the library more powerful and easier to use, and provide greater capabilities for debug. We are hard at work updating the reference library to match this new standard. Our goal is to have a functional library available for early adopters later this month and follow with the full reference implementation later this year.
After releasing the full implementation, the UVM Working Group will continue to provide ongoing maintenance for the library. We will also expand our efforts to include enhancements for potential contribution to future revisions of IEEE 1800.2, including addressing the inconsistencies between the UVM Register Layer and other standards (such as IP-XACT and SystemRDL).
We hope you will join us at DVCon U.S. 2018 later this month for our tutorial, “IEEE-Compatible UVM Reference Implementation and Verification Components,” where we will talk more in-depth about the new reference implementation and describe the new features and changes relative to UVM 1.2 and what they mean in real applications. We’ll address such questions as:
- What used to work that doesn’t anymore?
- How does the standard work now?
- What can I do now that I couldn’t before and what are the benefits of that?
The UVM Working Group is made up of dedicated volunteers helping to advance the standard. We are always looking for more members to help contribute so that we can get the work done faster. If you are an Accellera member and are interested in joining the UVM WG, please contact us.
Technical Spotlight: SystemC CCI
The SystemC CCI Configuration LRM draft standard is currently in public review. This standard defines both essential interfaces and convenience building blocks for configuring SystemC models in a way that enables compliant tools to set up, query, control, and track configuration information in a simple and effective manner. Supplemental materials in the review kit include an overview presentation, proof-of-concept implementation, and more than 20 examples.
The review period will remain open until March 18, 2018. Technical feedback and questions from the public can be posted to the Community Forum or emailed to
Portable Stimulus Community
We’ve added a new Portable Stimulus Community to our website. In this community you can access forum discussions, download tutorials and get the latest information about what’s happening with the emerging standard. If you have suggestions on what you’d like to see added to this community, please contact us.
SystemC Verification 2.0.1 Released
A new version of SystemC Verification is now available. It includes compatibility updates regarding SystemC 2.3.2 and newer compiler versions. Download SystemC Verification 2.0.1 >
SystemRDL 2.0 Released
SystemRDL is a Register Description Language for the design and delivery of IP products used in designs. Its semantics support the entire life-cycle of registers from specification, model generation, and design verification to maintenance and documentation. The need for SystemRDL continues to grow. Greater integration of SOCs has resulted in an explosion of registers and SystemRDL is the only standard for registers that supports the needs of both design capture and communication of register specs to downstream consumers. Download SystemRDL 2.0 >
In the News
Accellera announces its 2018 Board of Directors, Officers and Technical and Promotions Committee Chairs. For the complete list of board members, officers and committee chairs, read the full press release.
2018 Global Sponsors
Are you interested in becoming a Global Sponsor? Find out more about our Sponsorship Package.
Copyright 2018 Accellera Systems Initiative