Media Coverage

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2023

November 24th EDA standards for AI, China
eeNews Europe
October 31st DVCon Europe is Coming Soon - Sign Up Now
SemiWiki
October 26th Anatomy Of A System Simulation
Semiconductor Engineering
September 28th What Happened To Portable Stimulus?
Semiconductor Engineering
August 2nd Accellera and Clock Domain Crossing at #60DAC
SemiWiki
July 13th CHIPS Act, 3D-IC, AI, Open Source, and EDA-IP Tool Trends Dominate
Semiconductor Digest
June 29th Industry Organizations Are the Mainstay of the Semiconductor Ecosystem
EE Times Europe
May 1st Speeding the Path to Industry Standardization with Accellera
SemiWiki
March 16th Accellera Update at DVCon 2023
SemiWiki
January 19th What’s New in the 2022 IEEE IP-XACT Standard? Big Reveals from the Chair
Semiconductor Digest
January 13th Podcast: The International Impact of Accellera’s Work
SemiWiki

2022

November 23rd Weighing Chip-Design-Verification Challenges for MedTech
EE Times
October 4th Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development
Semiconductor Engineering
August 10th DAC – Where RISC-V Thrives and Mixed Signal Design Blends In
Electronics Weekly
July 29th Podcast: The History, Reach and Impact of Accellera with Lynn Garibaldi
SemiWiki
July 6th Accellera Update: CDC, Safety and AMS
SemiWiki
April 11th New Challenges For Connected Vehicles
Semiconductor Engineering
March 14th PSS in the Real World
Cadence Breakfast Bytes Blogs
March 10th DVCon Functional Safety
Cadence Breakfast Bytes Blogs
March 2nd DVCon: UVM Birds of a Feather
Cadence Breakfast Bytes Blogs
February 8th Accellera at DVCon U.S. 2022 in the Metaverse!
SemiWiki
January 11th Video: Pre-silicon D&V innovation and standardization efforts from Accellera
EDACafe Bunker Broadcast

2021

December 14th DAC 2021 – Accellera Panel all about Functional Safety Standards
SemiWiki
December 9th Design rules for functional safety are explored at DAC
Electronics Weekly
September 8th Functional Safety Working Group
Semiconductor Engineering
August 11th Challenges of Transitioning Back from Remote Work to Office
Pradeep's Techpoints
July 21st A Hardware Security Standard Advances
SemiWiki
June 23rd 5 Verification Engineers Provide Tips to Succeed When Working From Home
Design News
June 9th How easy is it building chips during a pandemic?
Pradeep's TechPoints
May 27th Accellera Unveils PSS 2.0 – Production Ready
SemiWiki
May 26th Functional Safety – What and How
SemiWiki
May 11th Accellera’s Functional Safety Group White Paper
Semiconductor Engineering
April 8th Interconnects In A Domain-Specific World
Semiconductor Engineering

2020

December 17th An Accellera Update. COVID Accelerates Progress
SemiWiki
October 14th IP Security Assurance Standard
Semiconductor Engineering
August 6th Accellera Tackles Functional Safety
Semiconductor Engineering
July 23rd Accellera IP Security Group Expects Standard by Year End
Tech Design Forum
July 10th Accellera’s Chair Highlights 2020 Events & Working Group Activity
EDACafe, Video Interview
May 5th Accellera Tackles Functional Safety, Mixed-Signal
SemiWiki
April 14th What is the Difference Between Test and Verification?
Design News
March 26th Standard Evolution
Semiconductor Engineering
March 26th Do You Trust Your IP Supplier?
Semiconductor Engineering
March 20th Create Once and Test Everywhere: The Promise of Portable Stimulus
Design News

2018

October 4th Accellera Tackles IP Security
SemiWiki
August 8th Agile Standards
Semiconductor Engineering
July 6th EDA Embraces Standard to Streamline IC Test and Verification
Electronics Weekly
July 2nd Tools Suppliers Back Version 1.0 of Portable Stimulus Standard
Tech Design Forum
February 1st DVCon US 2018 is Bigger and Better
EDACafe

2015

Summer 2015 Designing Efficiently for a Low Power World
EDACafe
March 5th DVCon: The Imitation Game
EDACafe
February 11th Accellera Systems Initiative Forms Portable Stimulus Working Group
Electronic Engineering Journal
February 11th Accellera Adds Portable Stimulus Group
Semiconductor Engineering