Universal Verification Methodology

UVM - Universal Verification Methodology

Universal Verification Methodology (UVM) is a standard to enable guaranteed development and reuse of verification environments and verification IP (VIP) throughout the electronics industry. Accellera provides both an API standard for UVM and a reference implementation. That reference implementation is a class library defined using the syntax and semantics of SystemVerilog (IEEE 1800).

  • Validated on multiple simulators
  • Scales from block to system level
  • Enhanced for multi-language verification
  • Standardized as UVM 1.2


UVM News

UVM 2.0 reference implementation has been updated to align with IEEE P1800.2-2020. Download it here >

UVM has an active user community. The LinkedIn group tops 14,800 members.

Found a bug or a have an enhancement request? Visit the UVM Community Forums.