Tutorial: UVM — What's Now and What's Next

UVM - Universal Verification Methodology

Presented at DVCon U.S. 2014 on March 3, 2014

The Universal Verification Methodology (UVM) has experienced great adoption and growth throughout the industry since its initial release as an Accellera standard three years ago. Verification engineers, EDA suppliers, service providers, and others throughout the electronics industry are actively creating verification environments following the UVM principles. Concepts like stimulus generation based on sequences, test execution using phases, communication based on transaction-level modeling (TLM), and the introduction of a register layer have all significantly contributed to the maturity of functional verification practices.

The presenters will share their experiences on both pragmatic topics that can be applied to UVM 1.1 and advanced topics for the next update of the standard. This tutorial will assume SystemVerilog language knowledge when discussing technical content and presenting detailed examples. Among the topics will be sequence creation, register layer use (both beginner and advanced), TLM-based communication, test execution using run-time phases, and messaging enhancements. All verification engineers — from those just starting to work with the UVM to those with years of experience — will gain new knowledge from the tutorials.

The tutorial is split into five sections:

  • Part 1: Part 1: UVM Working Group Update
    Adam Sherer, Accellera

  • Part 2: UVM Overview and Library Concepts
    John Aynsley, Doulos

  • Part 3: Stimulus Generation
    Shawn Honess, Synopsys

  • Part 4: UVM Register Layer
    Tom Fitzpatrick, Mentor Graphics

  • Part 5: UVM 1.2 Introduction
    Uwe Simm, Cadence

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