Tutorial: Next Generation Design and Verification Today

Presented at DVCon U.S. 2015 on March 2, 2015

When standards are applied in interesting ways to push the electronics industry they become much more than a language reference manual (LRM).  The working groups in Accellera are focused on solving specific problems key to raising the efficiency of our industry forming a design and verification foundation for us all to use.  However, the problems we need to solve often need more than one technology.  In that case, the community applies the existing standards in novel ways by connecting them together to solve next-generation problems today.

Mixed-signal verification is widely recognized as a growing challenge for modern semiconductors.  The tutorial will walk through a methodology that uniquely uses the power and architecture of the SystemVerilog UVM_REG to provide the necessary hooks to achieve constrained random stimulus during an AMS simulation thereby allowing the verification engineers to collect coverage automatically. Specific examples and lessons learned will be shared to emphasize how these techniques help in bridging the coverage gap between analog and digital interfaces which are the most challenging areas in the realm of mixed-signal verification.

Not only are huge projects in need of requirements-driven verification but some industries, like automotive have codified the need into their standards. Requirements-driven verification is similar to coverage-driven verification in the sense that it is metric-driven but differs significantly because the metrics derive from requirements rather than verification goals. Requirements-driven verification is also required for compliance with the increasing number of standards that control development of hardware for domains such as automotive (ISO26262) and avionics (DO254).  This tutorial will show how the UCIS can be in an automotive example to cover the three main issues regarding standards compliance and how they are covered through a requirements-driven verification methodology.

Power management for RTL and gates via the UPF standard, now IEEE 1801-2013, is widely used in the electronics industry.  With an increasing number of projects already moving to system level, or planning to in the near future, the P1801 working group is examining the next abstraction level as well.  This tutorial will examine this exciting next step for power management.

The tutorial is split into four sections:

  • Part 1: Part 1: Requirements-driven Verification Methodology (for Standards Compliance)
    Mike Bartley, TVS

  • Part 2: Using UCIS to Combine Verification Data from Multiple Tools
    Mike Bartley, TVS

  • Part 3: UVM REG: Path Towards Coverage Automation in AMS Simulations
    Kyle Newman, Texas Instruments

  • Part 4: New Developments in UPF 3.0
    Erich Marschner, Vice-Chair, IEEE P1801 WG

View slides >



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