The Language for System-Level Modeling, Design and Verification
SystemC® addresses the need for a system design and verification language that spans hardware and software. It is a language built in standard C++ by extending the language with the use of class libraries. The language is particularly suited to model system's partitioning, to evaluate and verify the assignment of blocks to either hardware or software implementations, and to architect and measure the interactions between and among functional blocks. Leading companies in the intellectual property (IP), electronic design automation (EDA), semiconductor, electronic systems, and embedded software industries currently use SystemC for architectural exploration, to deliver high-performance hardware blocks at various levels of abstraction and to develop virtual platforms for hardware/software co-design. SystemC was defined by the Open SystemC Initiative (OSCI) and ratified as IEEE Std. 1666™-2011.
An SoC is literally a system on a chip, consisting of both silicon and embedded software. Its design involves complex algorithm and architecture development and analysis similar to that performed in system design – a trade-off process that determines critical metrics, such as SOC performance, functionality, and power consumption.
Consequently, design tools must deliver orders-of-magnitude improvement in productivity at both architectural and implementation (RT and physical) levels. Moreover, tools must support a methodology that enables the early development of embedded application and system software, long before the availability of the RTL design or silicon prototype. Failure to achieve the requisite improvements in design productivity would result in missed market windows, and exploding design costs.
SystemC is a single, unified design and verification language that expresses architectural and other system-level attributes in the form of open-source C++ classes. It enables design and verification at the system level, independent of any detailed hardware and software implementation, as well as enabling co-verification with RTL design. This higher level of abstraction enables considerably faster, more productive architectural trade-off analysis, design, and redesign than is possible at the more detailed RT level. Furthermore, verification of system architecture and other system-level attributes is orders of magnitude faster than that at the pin-accurate, timing-accurate RT level.
The SystemC community consists of a large and growing number of system design companies, semiconductor companies, intellectual property providers, and EDA tool vendors who have joined together to support and promote the standard.
In July 2012, transaction-level modeling (TLM) was integrated into SystemC. TLM standard interfaces for SystemC provide an essential framework needed for model exchange within companies and across the IP supply chain for architecture analysis, software development and performance analysis, and hardware verification. It explicitly addresses virtual prototyping in which SystemC models can easily be exchanged and arranged within a system, enabling the optimal reuse of models and modeling effort across different use cases.
The SystemC AMS 2.0 standard introduces system-level design and modeling of embedded Analog/Mixed-Signal (AMS) systems. SystemC AMS provides unique capabilities for the design and modeling of embedded analog/mixed-signal applications at higher levels of design abstraction. The SystemC AMS extensions define a uniform and standardized modeling approach that can be used in combination with digitally-oriented ESL design methods, supporting a design refinement methodology for functional modeling, architecture exploration, and virtual prototyping of embedded analog/mixed-signal systems.
The goal of Configuration, Control and Inspection (CCI) is to improve efficiency and ROI for model creators and tool providers. They CCI standards will allow suppliers to instrument models so that a rich user experience is enabled, and they will allow industry tools to leverage this instrumentation to provide powerful debug and analysis capabilities. The CCI working group is currently defining standards for the exchange of information between SystemC models and tools.
The SystemC Verification (SCV) library provides a common set of APIs that are used as a basis to verification activities with SystemC (generation of values under constraints, transaction recording, etc.). These APIs are implemented in all major SystemC simulators available on the market.
- Tutorials and presentations:
- Video Tutorial: "SystemC: Focusing on High-Level Synthesis and Functional Coverage for SystemC" from DVCon U.S. 2019
- Panel Discussion: The future of the SystemC standard | Audio recorded at DVCon U.S. 2019
- Presentations: SystemC Evolution Day 2018 held on October 23, 2018
- Presentations: SystemC Evolution Day 2017 held on October 18, 2017
- Video Tutorial: "SystemC Design and Verification - Solidifying the Abstraction Above RTL" from DVCon U.S. 2017
- Video Tutorial: "Cut Your Design Time in Half with Higher Abstraction" from DVCon U.S. 2016
- Presentations: SystemC Evolution Day 2016 held on May 3, 2016
- Video Tutorial: "System-Level Modeling for Today and Tomorrow with SystemC" from DVCon Europe 2015
- Video tutorial: "SystemC Standardization Update Including UVM for SystemC" from DVCon 2015
- Video tutorial: "Increasing Productivity with SystemC in Complex System Design and Verification"
- SystemC Update delivered at NASCUG 19, DAC 2013
- Video tutorial: "An Introduction to IEEE 1666-2011, the New SystemC Standard"
- Video tutorial: "OSCI TLM-2.0 Standard and Synthesizable Subset"
- Numerous SystemC-related video presentations from NASCUG user group meetings
- SystemC User Groups