What is Tagging?
This standard provides a way to track both hard IP and non-hardened or soft IP information throughout the design and development process. The design process can include editing, synthesis, timing, placement, wiring, and other steps leading to GDS II generation. Semiconductor foundries, providers of IP Blocks, and manufacturers of design tools can use the methods described in this standard to track identification information throughout each level of the development process. At each level, tracking information is obtained from the previous level, and is transported to the next level using the appropriate output format.Note that this standard specifically addresses the passing of information throughout the design process. It does not consider the protection of the intellectual property (IP). The passing methods described in this standard are not secure, so they are potentially susceptible to tampering. These methods are intended only to facilitate the passing, use, and sharing of information among honest IP users and IP providers, helping to ensure the quality of the final design. Nevertheless, the mere existence of these methods does afford a low-level form of security.
What resources are available?
Hard IP Tagging Spec IPP 1 3.0 (Tags in GDSII)
Soft IP Tagging Spec IPP 4_2.0
TIPS
See the readme file before downloadingWhere did this come from?
