• Articles
• Events
• Presentations and Collateral

August 3, 2006 – A group of 15 leading European Semiconductor companies, Intellectual Property (IP) vendors, Electronic Design Automation (EDA) companies and academic institutions specializing in advanced silicon chip design today announced that they are working jointly in the SPRINT Project to keep Europe at the forefront of System-on-Chip (SoC) development. The project will develop new methodologies and standards to enable efficient reuse and exchange of IP to speed up and reduce costs of SoC design.

The SPRINT (Open SoC Design Platform for Reuse and Integration of IPs) Project is partly funded under the European Union’s IST Sixth Framework Program and partly by the project members. The alliance was started in February for an initial period of 30 months till mid-2008 to research and promote open interface and modeling standards for IP integration.

Project members include chipmakers Philips Semiconductors (including research groups at Philips Research), STMicroelectronics and Infineon Technologies; IP vendors ARM, Evatronix S.A., and Syosil; EDA vendors Spiratech Ltd, Lauterbach and KeesDA; research groups at Paderborn University, TIMA and the Royal Institute of Technology (KTH); and the ECSI association for training and dissemination.

The semiconductor industry can already fabricate phenomenally complex SoCs in the latest CMOS silicon processes. However, it is faced with spiraling design costs and shorter time-to-market SoC design requirements. Consequently, no single semiconductor or IP vendor can supply, in a time and cost efficient way, all the IP modules that need to be integrated into SoCs. Chip designers, therefore, have to pull together IP modules from several different vendors, adapt them to work together, and integrate them into their own designs. This process currently involves expensive and time-consuming manual design and verification. As a result, integration and reuse of IP from across vendor organizations is becoming a greater challenge for the semiconductor industry.

“The support of the EDA industry is critical to achieve increased abstraction and automation in SoC design,” said Wido Kruijtzer from Philips Semiconductors, Project Manager for the SPRINT Project. “Our annual SPRINT EDA Forum will give participating EDA vendors access to the SPRINT Project results and an opportunity to provide us feedback on our efforts.”


By building on existing initiatives such as OSCI (Open SystemC Initiative) SystemC / Transaction Level Modeling and The SPIRIT Consortium™ IP-XACT™ meta-data specifications and feeding its results back into these initiatives, the SPRINT Project will promote IP integration and reuse standards to enable automation across the design process. This will not only reduce the design cost but also shorten the time-to-market for next-generation SoCs.

Specific topics addressed within the SPRINT Project include:

• Techniques and standards for IP module modeling that allow the fast simulations required for architecture exploration and early software development, as well as provide reference models in SystemC/TLM for hardware functional verification
• Definition of standard communication interfaces that simplify the integration of IP modules while also resolving Quality-of-Service (QoS) issues
• Methodologies, libraries and tools to automate SoC design, verification and debug
  

Throughout all of this work, the project will generate a consistent design flow across multiple levels of abstraction, allowing results from one level to be reused at other levels.

About the SPRINT Project

The SPRINT Project is a European Union funded project in the IST Sixth Framework Programme that brings together the chip makers Philips Semiconductors (including research groups at Philips Research), STMicroelectronics and Infineon Technologies; IP vendors ARM, Evatronix S.A., and Syosil; EDA vendors, Spiratech Ltd, Lauterbach and KeesDA; research groups at Paderborn University, TIMA and the Royal Institute of Technology (KTH); and the ECSI association. The project will run for an initial period of 30 months. Building on existing infrastructures, the SPRINT Project will develop new methodologies and standards for interoperability and integration of the high-level IP modules from which modern SoC designs are assembled. More information on the SPRINT Project can be found at: www.sprint-project.net.

For more information please contact: