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Working Demonstrations at DATE 2007

Learn how The SPIRIT Consortium standards can improve SoC design efficiency today. See the IP-XACT specification in action on vendor tools and customer design-flows!

“Driving Innovation in Design-chain Integration: The SPIRIT Consortium
Standards and Partnership for Adoption"

Following the general update, overview, and TI adoption presentations, you'll be able to see the specification in the following working demonstrations:


Do you use configurable IP and tools from multiple vendors? Are you tired of transferring designs between tools by hand? Tools and IP are now inextricably linked and efficient IP integration demands efficient tool-flow integration. ARM use the IP-XACT standard to automatically link the system-level design tools RealView® SoC Designer and AMBA Designer into your hardware implementation and debug flows. The IP-XACT specification ensures that customers can leverage the benefits of ARM tools without the hassle of customized flow interoperability.


Cadence Design Systems will demonstrate generating IP-XACT assured descriptions for existing Intellectual Property directly from VHDL, Verilog, and SystemC. These descriptions will then be assembled and configured using IP-XACT designs and configurations. The resulting platform will be generated and simulated utilizing the Incisive Enterprise Simulator.

 


Denali will demonstrate the system-level register design and management capabilities of the Blueprint SystemRDL™ Compiler as it relates to consuming and producing IP-XACT XML. The demonstration will show actual IP-XACT XML for the Leon2 Processor being consumed by Blueprint.  Blueprint will then produce synthesizable RTL, specifications in HTML and FrameMaker, a SystemVerilog testbench, C and C++ files for software development, and IP-XACT assured XML files.

 


Bitwise is an integral part of Socrates, an open framework which complies with the IP-XACT specifications of The SPIRIT Consortium. This Eclipse-based framework offers SoC designers a development environment to enable rapid and effective SoC integration tasks. Socrates is a framework that allows concurrent engineering and provides a correct-by-construction environment.  Within Socrates there are many point tools that provide register management, IP integration and IO resolution of SoC data. Bitwise offers a highly sophisticated environment for importing, creating, and generating SoC register and memory-map related information.

 


Esterel Studio provides an automated path from ESL to RTL by generating consistent VHDL/Verilog and SystemC implementations from a single and formally verified Esterel Studio IP executable specification. Esterel Studio fully supports the IP-XACT specification from The SPIRIT Consortium to enable the generated design IP to be automatically integrated into architectural design, exploration and SoC integration tools. This demonstration shows the full benefits of ESL synthesis with the integration of an Esterel IP into ARM RealView® SoC Designer and Synopsys® coreAssembler.

 

  NXP Semiconductors
NXP uses and extends the IP-XACT v1.2 specification in the implementation of an ESL to RTL IC design flow.  The company’s goal is to extend the RTL design flow up to ESL abstraction including virtual prototyping.  While using IP-XACT v1.2 for RTL design, NXP is also contributing to further development of the IP-XACT specification within The SPIRIT Consortium working groups. NXP demo uses multiple tools to show current capabilities for RTL design using IP-XACT v1.2 and shows some early capabilities enabled by upcoming IP-XACT v1.4 features. The demo illustrates automated XML creation, design composition, and implementation at RTL and ESL.

 


Platform Express™ is the IP-XACT design environment that creates designs at the push of a button--creating designs and generating a range of targets enabling architectural exploration, design simulation, analysis, synthesis, and software development.  ARM and Mentor Graphics will demonstrate how sophisticated IP, documented using the IP-XACT XML databook format and Platform Express design environment, can be automatically integrated into a design and targeted at FPGA prototypes.

 


Synopsys will demonstrate the industry-leading DesignWare Cores in coreAssembler with its open API, native interfaces to the Galaxy™ and Discovery™ Platforms empowering an IP-XACT design flow. This flow is proven to speed IP integration and verification while achieving predictable success with significant design time reduction. The demo shows the creation of an AMBA® 3 IP-Subsystem containing DesignWare® Cores and verified with the AMBA 3 Assured Verification IP.