Working Demonstrations at DAC 2007
Learn how The SPIRIT Consortium standards can improve SoC design
efficiency today.
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ARM recognizes that tools and IP are inextricably linked
and that efficient IP integration demands efficient tool-flow integration.
ARM eliminates the error-prone transfer of designs between tools using
IP-XACT™ to automatically link its system-level design tools
RealView® SoC Designer and AMBA Designer into your hardware implementation and
debug flows. Deploying IP-XACT™ ensures that ARM customers can
leverage the benefits of ARM tools without the hassle of customized flow
interoperability.
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Beach Solutions is demonstrating a complete commercially
available System-on-Chip and system integration acceleration flow using
components and designs assured to conform to The SPIRIT Consortium IP-XACT
specification. Via the Beach EASI Tools
Suite graphical user interface, Beach Solutions demonstrates the capture of
various IP-XACT assured components; the validation of the data capture; and the
subsequent auto-generation of hardware, software, verification design and
integration files and a broad range of documentation formats.
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Cadence Design Systems’ demonstration generates
IP-XACT assured descriptions for existing Intellectual Property directly from
VHDL, Verilog, and SystemC. These descriptions are assembled and configured
using IP-XACT designs and configurations. The resulting platform is generated
and simulated utilizing the Incisive Enterprise Simulator.
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Denali is demonstrating the system-level register design
and management capabilities of the Blueprint SystemRDL™ Compiler as it relates
to consuming and producing IP-XACT XML. The demonstration will show actual
IP-XACT XML for the Leon2 Processor being consumed by Blueprint.
Blueprint will then produce synthesizable RTL, specifications in HTML and
FrameMaker, a SystemVerilog testbench, C and C++ files for software
development, and IP-XACT assured XML files.
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The Socrates SoC Integration
Framework from Duolog is an open Eclipse-based framework which utilizes the
IP-XACT specification from The SPIRIT Consortium to enable an interoperable
design flow for complex SoCs including register
management, IP capture, SoC IP assembly and IO resolution. This demonstration
shows a highly sophisticated environment for importing, creating, and
generating SoC register and memory map related information, as well as showing
IP interface standardization capabilities. The Socrates Generator framework is used
to show the auto-generation of various IP and SoC design and validation views.
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Improv Systems provides configurable DSP platforms
optimized for specific consumer applications such as video, audio, voice and
image processing. The Jazz Composer, an automation tool for configuring
these platforms, uses IP-XACT™ as its data base to represent and communicate
descriptions of these platforms. This presentation illustrates how the
configuration information is input to the system and used to generate complete
system descriptions in IP-XACT to design, and verify the platform.
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SPI-PACK 3.3, the IP-XACT packager from
Magillem Design Services, is used by several major companies as a
reference platform for creating and validating IP-XACT assured descriptions. Magillem
Design Services will demonstrate the fast and fully automated IP-XACT packaging
process for an SDRAM memory controller. Using Magillem 4.0, the packaged
component will be integrated in a LEON2-based platform. Magillem is a true
Eclipse 3.2 plug-in and provides a simple API for development of IP-XACT
assured generators.
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MataiTech demonstrates auto generation of documentation,
C/C++ HAL, SystemC, IP-XACT linting and semantic checking via MataiTech’s
flagship tool, NAUET (newt). The
demonstration will show NAUET’s IP-XACT Import Wizard that transforms your RTL
to IP-XACT and it will explore the many features of NAUET that accelerate HW/SW
co-development and debug. Attendees are
invited to bring IP-XACT files for an informal confidential lint during the
demonstration session.
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Platform Express is the IP-XACT design environment that, at the push of a
button, creates designs and associated testbenches. Platform
Express generates a range of targets enabling design verification,
architectural exploration, analysis, synthesis, and software development.
Mentor Graphics will demonstrate how the IP-XACT XML databook format can be
used to automate the construction of designs and
transaction-level testbenches employing advanced verification
methodologies, including languages such as SystemC and SystemC Verilog.
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NXP uses and extends the IP-XACT specification to
implement an ESL to RTL IC design flow. While using IP-XACT for RTL
design today, the company’s goal contributes within The SPIRIT Consortium to
extend the RTL design flow up to ESL abstraction including virtual
prototyping. NXP will demonstrate multi-vendor tool integration to show
current capabilities for RTL design using IP-XACT as well as some early
capabilities enabled by upcoming features of IP-XACT with ESL Extensions.
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Scarlet's Component Foundry is a low-cost
IP-XACT component creation tool, which will create IP-XACT descriptions
straight from legacy IP, parsing information straight from RTL files and PDF
documents, creating IP-XACT files in seconds. The intuitive GUI and semantic
checker offer easy and accurate editing of IP-XACT components. No knowledge of
XML is required, and wizards are available where user input is required. The
tool intelligently highlights missing files and data.
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Synopsys is demonstrating the industry-leading DesignWare
Cores in coreAssembler with its open API, native interfaces to the Galaxy™ and
Discovery™ Platforms empowering an IP-XACT design flow. This flow is proven to
speed IP integration and verification while achieving predictable success with
significant design time reduction. The demo shows the creation of an AMBA® 3
IP-Subsystem containing DesignWare® Cores and verified with the AMBA 3 Assured
Verification IP.