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Partner Demonstrations from The SPIRIT Consortium General Session at DAC


ARM: Multi-stage design-flow integration from SystemC, to RTL, to prototype-board debug configuration using IP-XACT
  • Demo Host:Nizar Romdhane, ESL Technical Marketing Manager
  • Abstract:Today's multi-stage SoC flows must represent designs in multiple ways, from SystemC models, to co-verification and implementation views, through to hard prototypes for full system integration. We show how system meta-data descriptions using IP-XACT from The SPIRIT Consortium can be used to exchange system architectures between RealView® SoC Designer, a SystemC environment, to RTL design and verification environments from Mentor Graphics and Synopsys, as well as configure RealView RVI debug for hard-prototype targets.

Beach Solutions: IP-XACT used to drive IP verification using Beach Solution's EASI-Studio tool

  • Demo Host: Colin Tattersall, CTO
  • Abstract:Beach Solutions demonstrate the import of IP into its EASI-Studio SoC product using the IP-XACT specifications from The SPIRIT Consortium, and the subsequent generation of debug and verification views from the IP-XACT meta-data. Beach also demonstrate the reuseability of meta-data stored in IP-XACT format, and show that by standardizing IP meta-data in this format there are huge gains to be made today in automating development flows, and improving the quality of the delivered IP.

Denali: Denali’s Blueprint demonstration: SystemRDL and IP-XACT - language synergy for combining IP

  • Demo Host: Sean Smith, Chief Verification Architect
  • Abstract:A key challenge being addressed by IP-XACT schema from The SPIRIT Consortium and SystemRDL is combining IP from various sources. Blueprint eases register definition and IP integration by supporting these high-level system-design languages and exchange formats for automating the creation and management of control registers, related models, design views, and documentation. In-house legacy, IP vendor, and system-level register specification definitions are all consumed to generate consistent views of registers targeted for all design teams, test groups, and customers. Blueprint generates views for ESL, HW/SW development, verification, and documentation with supported output formats including IP-XACT, Verilog, C, C++, OpenVera, e, OVL, Frame, HTML, MS-Word, and more.

Esterel Technologies: ESL synthesis with Esterel Studio and The SPIRIT Consortium specifications

  • Demo Host: Arnaldo Malavasi, Senior FAE
  • Abstract:Esterel Studio provides an automated path from ESL to RTL by generating consistent VHDL/Verilog and SystemC implementations from a single and formally verified Esterel Studio IP executable specification. Now that Esterel Studio fully supports the IP-XACT specification from The SPIRIT Consortium, SoC Architects and Designers can quickly import Esterel Studio designed IP into their architectural design, exploration and SoC integration tools. Our demonstration shows the full benefits of ESL synthesis with the integration of an Esterel IP into ARM RealView® SoC Designer and Synopsys® coreAssembler.

Improv Systems: Integration and Configuration of The Improv Media Platform Using IP-XACT

  • Demo Host: Cary Ussery, President and CEO
  • Abstract:The Improv Media Platform is a highly configurable multi-processor subsystem designed to accelerate algorithms such as MPEG4 and H264. The Andante SoC Development System implements complex heterogeneous multi-core SoCs using constraint driven IP data and software centric scheduling. To configure each customized subsystem, the Improv Development System uses the power of the IP-XACT specification from The SPIRIT Consortium in building generators to automate the development, analysis, and verification of the subsystem and its integration into the SoC

Mentor Graphics: Platform Express: An IP-XACT design environment for system level design and verification

  • Demo Host: John Wilson, Product Architect
  • Abstract:Platform Express is the first Design Environment to deliver support for The SPIRIT Consortium's v1.2 IP-XACT specification. Taking advantage of new Verification IP capabilities in IP-XACT, a wide range of assertions and protocol monitors are now supported as part of the automated design creation process. Coupled with existing capabilities to generate HDL (both RTL and ESL), software, documentation, support for a wide range of design tools, and easy extensibility, Platform Express is the leading Design Environment enabling full exploitation of IP-XACT XML information in your design flow. Download it and start designing : www.mentor.com/platform_express.

Philips Semiconductors: Creating an efficient derivative design flow using the IP-XACT specification

  • Demo Host: Marino Strik, Senior IC Architect
  • Abstract:By building on reuse methodologies and standards, Philips Semiconductors sees an enormous potential to shorten the design cycle for IC derivatives. A necessity is that a repository of IP from multiple sources is available. The properties of the components in this repository must be described in a common way so that methods for creating derivatives can be automated, including IP configuration and integration. This, with EDA tools support, is where the IP-XACT specification of The SPIRIT Consortium is playing an enabling role.

Poseidon-Systems: Performance Matters: Standards help in analyzing the performance characteristics of an embedded system

  • Demo Host: Bill Salefski, VP of Technical Marketing
  • Abstract:Today’s systems are both large and composed of many blocks that have complex, performance-limiting interactions. The Triton tools from Poseidon Design Systems read system architectures described with IP-XACT from The SPIRIT Consortium. The system is simulated and bottlenecks pinpointed in Triton Tuner, a SystemC-based, transaction-based simulator. The bottlenecks are relieved by optimizing the code using the Triton Tuner analysis tools, or using Triton Builder to add hardware acceleration.

Synopsys: An Integrated IP-XACT Design and Verification flow with Synopsys’ coreAssembler and DesignWare IP

  • Demo Host: John A. Swanson, Senior Manager
  • Abstract:Synopsys will demonstrate coreAssembler with native interfaces to the Galaxy™ and Discovery™ Platforms driving an IP-XACT design and verification flow easing the process of IP integration while achieving predictable success with significant design time reduction. The demo will show the creation of a PCI Express® AMBA® 3 IP-Subsystem containing the DesignWare® PCI Express Core, AMBA 3 Assured Verification IP and DesignWare Synthesizable IP for AMBA 3 AXI™ using coreAssembler.